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/first 4335 0 r /parent 4289 0 r /next 4331 0 r /dest (g1.1832214) /count -10 /last 4336 0 r /prev 4337 0 r /title (14. timer/counter0) >> endobj 4335 0 obj << /parent 4334 0 r /next 4487 0 r /dest (g1.1832215) /title (14.1 features) >> endobj 4336 0 obj << /first 4471 0 r /parent 4334 0 r /dest (g1.1832623) /count -7 /last 4472 0 r /prev 4473 0 r /title (14.10 register description) >> endobj 4337 0 obj << /first 4338 0 r /parent 4289 0 r /next 4334 0 r /dest (g1.1831959) /count -3 /last 4339 0 r /prev 4340 0 r /title (13. timer/counter0 prescaler) >> endobj 4338 0 obj << /parent 4337 0 r /next 4470 0 r /dest (g1.1831961) /title (13.0.1 prescaler reset) >> endobj 4339 0 obj << /first 4469 0 r /parent 4337 0 r /dest (g1.1832013) /count -1 /last 4469 0 r /prev 4470 0 r /title (13.1 register description) >> endobj 4340 0 obj << /first 4341 0 r /parent 4289 0 r /next 4337 0 r /dest (g1.1182705) /count -4 /last 4342 0 r /prev 4343 0 r /title (12. i/o ports) >> endobj 4341 0 obj << /parent 4340 0 r /next 4457 0 r /dest (g1.1182706) /title (12.1 overview) >> endobj 4342 0 obj << /first 4452 0 r /parent 4340 0 r /dest (g1.1874089) /count -7 /last 4453 0 r /prev 4454 0 r /title (12.4 register description) >> endobj 4343 0 obj << /first 4344 0 r /parent 4289 0 r /next 4340 0 r /dest (g1.1738372) /count -1 /last 4344 0 r /prev 4345 0 r /title (11. external interrupts) >> endobj 4344 0 obj << /first 4447 0 r /parent 4343 0 r /dest (g1.1978115) /count -5 /last 4448 0 r /title (11.1 register description) >> endobj 4345 0 obj << /first 4346 0 r /parent 4289 0 r /next 4343 0 r /dest (g1.1182217) /count -1 /last 4346 0 r /prev 4347 0 r /title (10. interrupts) >> endobj 4346 0 obj << /parent 4345 0 r /dest (g1.1182226) /title (10.1 interrupt vectors in attiny261/461/861) >> endobj 4347 0 obj << /first 4348 0 r /parent 4289 0 r /next 4345 0 r /dest (g1.1181426) /count -10 /last 4349 0 r /prev 4350 0 r /title (9. system control and reset) >> endobj 4348 0 obj << /parent 4347 0 r /next 4446 0 r /dest (g1.1181427) /title (9.0.1 resetting the avr) >> endobj 4349 0 obj << /first 4434 0 r /parent 4347 0 r /dest (g1.1974599) /count -2 /last 4435 0 r /prev 4436 0 r /title (9.4 register description) >> endobj 4350 0 obj << /first 4351 0 r /parent 4289 0 r /next 4347 0 r /dest (g1.1551528) /count -8 /last 4352 0 r /prev 4353 0 r /title (8. power management and sleep modes) >> endobj 4351 0 obj << /parent 4350 0 r /next 4429 0 r /dest (g1.1970952) /title (8.1 sleep modes) >> endobj 4352 0 obj << /first 4420 0 r /parent 4350 0 r /dest (g1.1964848) /count -2 /last 4421 0 r /prev 4422 0 r /title (8.8 register description) >> endobj 4353 0 obj << /first 4354 0 r /parent 4289 0 r /next 4350 0 r /dest (g1.1922109) /count -12 /last 4355 0 r /prev 4356 0 r /title (7. system clock and clock options) >> endobj 4354 0 obj << /first 4415 0 r /parent 4353 0 r /next 4414 0 r /dest (g1.1179921) /count -5 /last 4416 0 r /title (7.1 clock systems and their distribution) >> endobj 4355 0 obj << /first 4402 0 r /parent 4353 0 r /dest (g1.1962835) /count -2 /last 4403 0 r /prev 4404 0 r /title (7.12 register description) >> endobj 4356 0 obj << /first 4357 0 r /parent 4289 0 r /next 4353 0 r /dest (g1.1179079) /count -5 /last 4358 0 r /prev 4359 0 r /title (6. avr memories) >> endobj 4357 0 obj << /parent 4356 0 r /next 4392 0 r /dest (g1.1179087) /title (6.1 in-system re-programmable flash program memory) >> endobj 4358 0 obj << /first 4385 0 r /parent 4356 0 r /dest (g1.1955937) /count -6 /last 4386 0 r /prev 4387 0 r /title (6.5 register description) >> endobj 4359 0 obj << /first 4360 0 r /parent 4289 0 r /next 4356 0 r /dest (g1.1178410) /count -7 /last 4361 0 r /prev 4362 0 r /title (5. avr cpu core) >> endobj 4360 0 obj << /parent 4359 0 r /next 4384 0 r /dest (g1.1178411) /title (5.1 overview) >> endobj 4361 0 obj << /first 4376 0 r /parent 4359 0 r /dest (g1.1179018) /count -1 /last 4376 0 r /prev 4377 0 r /title (5.7 reset and interrupt handling) >> endobj 4362 0 obj << /parent 4289 0 r /next 4359 0 r /dest (g1.1785777) /prev 4363 0 r /title (4. about code examples) >> endobj 4363 0 obj << /parent 4289 0 r /next 4362 0 r /dest (g1.1907218) /prev 4364 0 r /title (3. resources) >> endobj 4364 0 obj << /first 4365 0 r /parent 4289 0 r /next 4363 0 r /dest (g1.1178304) /count -2 /last 4366 0 r /prev 4367 0 r /title (2. overview) >> endobj 4365 0 obj << /parent 4364 0 r /next 4366 0 r /dest (g1.1178312) /title (2.1 block diagram) >> endobj 4366 0 obj << /first 4369 0 r /parent 4364 0 r /dest (g1.1178330) /count -7 /last 4370 0 r /prev 4365 0 r /title (2.2 pin descriptions) >> endobj 4367 0 obj << /first 4368 0 r /parent 4289 0 r /next 4364 0 r /dest (g1.1782036) /count -1 /last 4368 0 r /prev 4290 0 r /title (1. pin configurations) >> endobj 4368 0 obj << /parent 4367 0 r /dest (g1.1258121) /title (1.1 disclaimer) >> endobj 4369 0 obj << /parent 4366 0 r /next 4375 0 r /dest (g1.1178331) /title (2.2.1 vcc) >> endobj 4370 0 obj << /parent 4366 0 r /dest (g1.1178393) /prev 4371 0 r /title (2.2.7 reset) >> endobj 4371 0 obj << /parent 4366 0 r /next 4370 0 r /dest (g1.1785727) /prev 4372 0 r /title (2.2.6 port b \(pb7..pb0\)) >> endobj 4372 0 obj << /parent 4366 0 r /next 4371 0 r /dest (g1.1178344) /prev 4373 0 r /title (2.2.5 port a \(pa7..pa0\)) >> endobj 4373 0 obj << /parent 4366 0 r /next 4372 0 r /dest (g1.1785085) /prev 4374 0 r /title (2.2.4 agnd) >> endobj 4374 0 obj << /parent 4366 0 r /next 4373 0 r /dest (g1.1785083) /prev 4375 0 r /title (2.2.3 avcc) >> endobj 4375 0 obj << /parent 4366 0 r /next 4374 0 r /dest (g1.1178333) /prev 4369 0 r /title (2.2.2 gnd) >> endobj 4376 0 obj << /parent 4361 0 r /dest (g1.1179073) /title (5.7.1 interrupt response time) >> endobj 4377 0 obj << /parent 4359 0 r /next 4361 0 r /dest (g1.1178997) /prev 4378 0 r /title (5.6 instruction execution timing) >> endobj 4378 0 obj << /first 4379 0 r /parent 4359 0 r /next 4377 0 r /dest (g1.1178830) /count -1 /last 4379 0 r /prev 4380 0 r /title (5.5 stack pointer) >> endobj 4379 0 obj << /parent 4378 0 r /dest (g1.1907938) /title (5.5.1 sph and spl - stack pointer register) >> endobj 4380 0 obj << /first 4381 0 r /parent 4359 0 r /next 4378 0 r /dest (g1.1907997) /count -1 /last 4381 0 r /prev 4382 0 r /title (5.4 general purpose register file) >> endobj 4381 0 obj << /parent 4380 0 r /dest (g1.1953633) /title (5.4.1 the x-register, y-register, and z-register) >> endobj 4382 0 obj << /first 4383 0 r /parent 4359 0 r /next 4380 0 r /dest (g1.1178435) /count -1 /last 4383 0 r /prev 4384 0 r /title (5.3 status register) >> endobj 4383 0 obj << /parent 4382 0 r /dest (g1.1907929) /title (5.3.1 sreg - avr status register) >> endobj 4384 0 obj << /parent 4359 0 r /next 4382 0 r /dest (g1.1178432) /prev 4360 0 r /title (5.2 alu - arithmetic logic unit) >> endobj 4385 0 obj << /parent 4358 0 r /next 4401 0 r /dest (g1.1955946) /title (6.5.1 eearh and eearl - eeprom address register) >> endobj 4386 0 obj << /parent 4358 0 r /dest (g1.1922305) /prev 4398 0 r /title (6.5.6 gpior0 - general purpose i/o register 0) >> endobj 4387 0 obj << /first 4388 0 r /parent 4356 0 r /next 4358 0 r /dest (g1.1179646) /count -1 /last 4388 0 r /prev 4389 0 r /title (6.4 i/o memory) >> endobj 4388 0 obj << /parent 4387 0 r /dest (g1.1922125) /title (6.4.1 general purpose i/o registers) >> endobj 4389 0 obj << /first 4390 0 r /parent 4356 0 r /next 4387 0 r /dest (g1.1179150) /count -6 /last 4391 0 r /prev 4392 0 r /title (6.3 eeprom data memory) >> endobj 4390 0 obj << /parent 4389 0 r /next 4397 0 r /dest (g1.1179163) /title (6.3.1 eeprom read/write access) >> endobj 4391 0 obj << /parent 4389 0 r /dest (g1.1179639) /prev 4394 0 r /title (6.3.6 preventing eeprom corruption) >> endobj 4392 0 obj << /first 4393 0 r /parent 4356 0 r /next 4389 0 r /dest (g1.1179111) /count -1 /last 4393 0 r /prev 4357 0 r /title (6.2 sram data memory) >> endobj 4393 0 obj << /parent 4392 0 r /dest (g1.1179140) /title (6.2.1 data memory access times) >> endobj 4394 0 obj << /parent 4389 0 r /next 4391 0 r /dest (g1.1504066) /prev 4395 0 r /title (6.3.5 write) >> endobj 4395 0 obj << /parent 4389 0 r /next 4394 0 r /dest (g1.1504058) /prev 4396 0 r /title (6.3.4 erase) >> endobj 4396 0 obj << /parent 4389 0 r /next 4395 0 r /dest (g1.1504049) /prev 4397 0 r /title (6.3.3 split byte programming) >> endobj 4397 0 obj << /parent 4389 0 r /next 4396 0 r /dest (g1.1504039) /prev 4390 0 r /title (6.3.2 atomic byte programming) >> endobj 4398 0 obj << /parent 4358 0 r /next 4386 0 r /dest (g1.1922218) /prev 4399 0 r /title (6.5.5 gpior1 - general purpose i/o register 1) >> endobj 4399 0 obj << /parent 4358 0 r /next 4398 0 r /dest (g1.1922131) /prev 4400 0 r /title (6.5.4 gpior2 - general purpose i/o register 2) >> endobj 4400 0 obj << /parent 4358 0 r /next 4399 0 r /dest (g1.1956222) /prev 4401 0 r /title (6.5.3 eecr - eeprom control register) >> endobj 4401 0 obj << /parent 4358 0 r /next 4400 0 r /dest (g1.1957073) /prev 4385 0 r /title (6.5.2 eedr - eeprom data register) >> endobj 4402 0 obj << /parent 4355 0 r /next 4403 0 r /dest (g1.1957119) /title (7.12.1 osccal - oscillator calibration register) >> endobj 4403 0 obj << /parent 4355 0 r /dest (g1.1959861) /prev 4402 0 r /title (7.12.2 clkpr - clock prescale register) >> endobj 4404 0 obj << /first 4405 0 r /parent 4353 0 r /next 4355 0 r /dest (g1.1687485) /count -1 /last 4405 0 r /prev 4406 0 r /title (7.11 system clock prescaler) >> endobj 4405 0 obj << /parent 4404 0 r /dest (g1.1551539) /title (7.11.1 switching time) >> endobj 4406 0 obj << /parent 4353 0 r /next 4404 0 r /dest (g1.1689611) /prev 4407 0 r /title (7.10 clock output buffer) >> endobj 4407 0 obj << /parent 4353 0 r /next 4406 0 r /dest (g1.1601452) /prev 4408 0 r /title (7.9 crystal oscillator) >> endobj 4408 0 obj << /parent 4353 0 r /next 4407 0 r /dest (g1.1792215) /prev 4409 0 r /title (7.8 low-frequency crystal oscillator) >> endobj 4409 0 obj << /parent 4353 0 r /next 4408 0 r /dest (g1.1792113) /prev 4410 0 r /title (7.7 128 khz internal oscillator) >> endobj 4410 0 obj << /parent 4353 0 r /next 4409 0 r /dest (g1.1934781) /prev 4411 0 r /title (7.6 calibrated internal rc oscillator) >> endobj 4411 0 obj << /parent 4353 0 r /next 4410 0 r /dest (g1.1789010) /prev 4412 0 r /title (7.5 high frequency pll clock - pllclk) >> endobj 4412 0 obj << /parent 4353 0 r /next 4411 0 r /dest (g1.1788942) /prev 4413 0 r /title (7.4 external clock) >> endobj 4413 0 obj << /parent 4353 0 r /next 4412 0 r /dest (g1.1590128) /prev 4414 0 r /title (7.3 default clock source) >> endobj 4414 0 obj << /parent 4353 0 r /next 4413 0 r /dest (g1.1590077) /prev 4354 0 r /title (7.2 clock sources) >> endobj 4415 0 obj << /parent 4354 0 r /next 4419 0 r /dest (g1.1179933) /title (7.1.1 cpu clock - clkcpu) >> endobj 4416 0 obj << /parent 4354 0 r /dest (g1.1571499) /prev 4417 0 r /title (7.1.5 internal pll for fast peripheral clock generation - clkpck) >> endobj 4417 0 obj << /parent 4354 0 r /next 4416 0 r /dest (g1.1179941) /prev 4418 0 r /title (7.1.4 adc clock - clkadc) >> endobj 4418 0 obj << /parent 4354 0 r /next 4417 0 r /dest (g1.1179937) /prev 4419 0 r /title (7.1.3 flash clock - clkflash) >> endobj 4419 0 obj << /parent 4354 0 r /next 4418 0 r /dest (g1.1179935) /prev 4415 0 r /title (7.1.2 i/o clock - clki/o) >> endobj 4420 0 obj << /parent 4352 0 r /next 4421 0 r /dest (g1.1964857) /title (8.8.1 mcucr - mcu control register) >> endobj 4421 0 obj << /parent 4352 0 r /dest (g1.1967522) /prev 4420 0 r /title (8.8.2 prr - power reduction register) >> endobj 4422 0 obj << /first 4423 0 r /parent 4350 0 r /next 4352 0 r /dest (g1.1660962) /count -6 /last 4424 0 r /prev 4425 0 r /title (8.7 minimizing power consumption) >> endobj 4423 0 obj << /parent 4422 0 r /next 4433 0 r /dest (g1.1181388) /title (8.7.1 analog to digital converter) >> endobj 4424 0 obj << /parent 4422 0 r /dest (g1.1181413) /prev 4430 0 r /title (8.7.6 port pins) >> endobj 4425 0 obj << /parent 4350 0 r /next 4422 0 r /dest (g1.1663052) /prev 4426 0 r /title (8.6 power reduction register) >> endobj 4426 0 obj << /parent 4350 0 r /next 4425 0 r /dest (g1.1792939) /prev 4427 0 r /title (8.5 standby mode) >> endobj 4427 0 obj << /parent 4350 0 r /next 4426 0 r /dest (g1.1490269) /prev 4428 0 r /title (8.4 power-down mode) >> endobj 4428 0 obj << /parent 4350 0 r /next 4427 0 r /dest (g1.1490263) /prev 4429 0 r /title (8.3 adc noise reduction mode) >> endobj 4429 0 obj << /parent 4350 0 r /next 4428 0 r /dest (g1.1475469) /prev 4351 0 r /title (8.2 idle mode) >> endobj 4430 0 obj << /parent 4422 0 r /next 4424 0 r /dest (g1.1181408) /prev 4431 0 r /title (8.7.5 watchdog timer) >> endobj 4431 0 obj << /parent 4422 0 r /next 4430 0 r /dest (g1.1551561) /prev 4432 0 r /title (8.7.4 internal voltage reference) >> endobj 4432 0 obj << /parent 4422 0 r /next 4431 0 r /dest (g1.1181398) /prev 4433 0 r /title (8.7.3 brown-out detector) >> endobj 4433 0 obj << /parent 4422 0 r /next 4432 0 r /dest (g1.1181393) /prev 4423 0 r /title (8.7.2 analog comparator) >> endobj 4434 0 obj << /parent 4349 0 r /next 4435 0 r /dest (g1.1974608) /title (9.4.1 mcusr - mcu status register) >> endobj 4435 0 obj << /parent 4349 0 r /dest (g1.1977070) /prev 4434 0 r /title (9.4.2 wdtcr - watchdog timer control register) >> endobj 4436 0 obj << /first 4437 0 r /parent 4347 0 r /next 4349 0 r /dest (g1.1907901) /count -2 /last 4438 0 r /prev 4439 0 r /title (9.3 timed sequences for changing the configuration of the watchdog timer) >> endobj 4437 0 obj << /parent 4436 0 r /next 4438 0 r /dest (g1.1182208) /title (9.3.1 safety level 1) >> endobj 4438 0 obj << /parent 4436 0 r /dest (g1.1182212) /prev 4437 0 r /title (9.3.2 safety level 2) >> endobj 4439 0 obj << /parent 4347 0 r /next 4436 0 r /dest (g1.1181875) /prev 4440 0 r /title (9.2 watchdog timer) >> endobj 4440 0 obj << /first 4441 0 r /parent 4347 0 r /next 4439 0 r /dest (g1.1552928) /count -1 /last 4441 0 r /prev 4442 0 r /title (9.1 internal voltage reference) >> endobj 4441 0 obj << /parent 4440 0 r /dest (g1.1552933) /title (9.1.1 voltage reference enable signals and start-up time) >> endobj 4442 0 obj << /parent 4347 0 r /next 4440 0 r /dest (g1.1181678) /prev 4443 0 r /title (9.0.6 watchdog reset) >> endobj 4443 0 obj << /parent 4347 0 r /next 4442 0 r /dest (g1.1181656) /prev 4444 0 r /title (9.0.5 brown-out detection) >> endobj 4444 0 obj << /parent 4347 0 r /next 4443 0 r /dest (g1.1181646) /prev 4445 0 r /title (9.0.4 external reset) >> endobj 4445 0 obj << /parent 4347 0 r /next 4444 0 r /dest (g1.1181631) /prev 4446 0 r /title (9.0.3 power-on reset) >> endobj 4446 0 obj << /parent 4347 0 r /next 4445 0 r /dest (g1.1181440) /prev 4348 0 r /title (9.0.2 reset sources) >> endobj 4447 0 obj << /parent 4344 0 r /next 4451 0 r /dest (g1.1738383) /title (11.1.1 mcucr - mcu control register) >> endobj 4448 0 obj << /parent 4344 0 r /dest (g1.1805575) /prev 4449 0 r /title (11.1.5 pcmsk1 - pin change mask register b) >> endobj 4449 0 obj << /parent 4344 0 r /next 4448 0 r /dest (g1.1805487) /prev 4450 0 r /title (11.1.4 pcmsk0 - pin change mask register a) >> endobj 4450 0 obj << /parent 4344 0 r /next 4449 0 r /dest (g1.1738615) /prev 4451 0 r /title (11.1.3 gifr - general interrupt flag register) >> endobj 4451 0 obj << /parent 4344 0 r /next 4450 0 r /dest (g1.1908249) /prev 4447 0 r /title (11.1.2 gimsk - general interrupt mask register) >> endobj 4452 0 obj << /parent 4342 0 r /next 4468 0 r /dest (g1.1978132) /title (12.4.1 mcucr - mcu control register) >> endobj 4453 0 obj << /parent 4342 0 r /dest (g1.1185723) /prev 4464 0 r /title (12.4.7 pinb - port b input pins address) >> endobj 4454 0 obj << /first 4455 0 r /parent 4340 0 r /next 4342 0 r /dest (g1.1182921) /count -2 /last 4456 0 r /prev 4457 0 r /title (12.3 alternate port functions) >> endobj 4455 0 obj << /parent 4454 0 r /next 4456 0 r /dest (g1.1808870) /title (12.3.1 alternate functions of port b) >> endobj 4456 0 obj << /parent 4454 0 r /dest (g1.1818240) /prev 4455 0 r /title (12.3.2 alternate functions of port a) >> endobj 4457 0 obj << /first 4458 0 r /parent 4340 0 r /next 4454 0 r /dest (g1.1182734) /count -6 /last 4459 0 r /prev 4341 0 r /title (12.2 ports as general digital i/o) >> endobj 4458 0 obj << /parent 4457 0 r /next 4463 0 r /dest (g1.1182750) /title (12.2.1 configuring the pin) >> endobj 4459 0 obj << /parent 4457 0 r /dest (g1.1553391) /prev 4460 0 r /title (12.2.6 unconnected pins) >> endobj 4460 0 obj << /parent 4457 0 r /next 4459 0 r /dest (g1.1182910) /prev 4461 0 r /title (12.2.5 digital input enable and sleep modes) >> endobj 4461 0 obj << /parent 4457 0 r /next 4460 0 r /dest (g1.1182850) /prev 4462 0 r /title (12.2.4 reading the pin value) >> endobj 4462 0 obj << /parent 4457 0 r /next 4461 0 r /dest (g1.1324872) /prev 4463 0 r /title (12.2.3 switching between input and output) >> endobj 4463 0 obj << /parent 4457 0 r /next 4462 0 r /dest (g1.1324868) /prev 4458 0 r /title (12.2.2 toggling the pin) >> endobj 4464 0 obj << /parent 4342 0 r /next 4453 0 r /dest (g1.1185639) /prev 4465 0 r /title (12.4.6 ddrb - port b data direction register) >> endobj 4465 0 obj << /parent 4342 0 r /next 4464 0 r /dest (g1.1185555) /prev 4466 0 r /title (12.4.5 portb - port b data register) >> endobj 4466 0 obj << /parent 4342 0 r /next 4465 0 r /dest (g1.1821140) /prev 4467 0 r /title (12.4.4 pina - port a input pins address) >> endobj 4467 0 obj << /parent 4342 0 r /next 4466 0 r /dest (g1.1821056) /prev 4468 0 r /title (12.4.3 ddra - port a data direction register) >> endobj 4468 0 obj << /parent 4342 0 r /next 4467 0 r /dest (g1.1820972) /prev 4452 0 r /title (12.4.2 porta - port a data register) >> endobj 4469 0 obj << /parent 4339 0 r /dest (g1.1980338) /title (13.1.1 tccr0b - timer/counter0 control register b) >> endobj 4470 0 obj << /parent 4337 0 r /next 4339 0 r /dest (g1.1831964) /prev 4338 0 r /title (13.0.2 external clock source) >> endobj 4471 0 obj << /parent 4336 0 r /next 4498 0 r /dest (g1.1832625) /title (14.10.1 tccr0a - timer/counter0 control register a) >> endobj 4472 0 obj << /parent 4336 0 r /dest (g1.1908486) /prev 4494 0 r /title (14.10.7 tifr - timer/counter0 interrupt flag register) >> endobj 4473 0 obj << /first 4474 0 r /parent 4334 0 r /next 4336 0 r /dest (g1.1832518) /count -1 /last 4474 0 r /prev 4475 0 r /title (14.9 accessing registers in 16-bit mode) >> endobj 4474 0 obj << /parent 4473 0 r /dest (g1.1832620) /title (14.9.1 reusing the temporary high byte register) >> endobj 4475 0 obj << /parent 4334 0 r /next 4473 0 r /dest (g1.1832483) /prev 4476 0 r /title (14.8 timer/counter timing diagrams) >> endobj 4476 0 obj << /first 4477 0 r /parent 4334 0 r /next 4475 0 r /dest (g1.1832407) /count -2 /last 4478 0 r /prev 4479 0 r /title (14.7 output compare unit) >> endobj 4477 0 obj << /parent 4476 0 r /next 4478 0 r /dest (g1.1832417) /title (14.7.1 compare match blocking by tcnt0 write) >> endobj 4478 0 obj << /parent 4476 0 r /dest (g1.1832431) /prev 4477 0 r /title (14.7.2 using the output compare unit) >> endobj 4479 0 obj << /first 4480 0 r /parent 4334 0 r /next 4476 0 r /dest (g1.1933013) /count -3 /last 4481 0 r /prev 4482 0 r /title (14.6 input capture unit) >> endobj 4480 0 obj << /parent 4479 0 r /next 4493 0 r /dest (g1.1934447) /title (14.6.1 input capture trigger source) >> endobj 4481 0 obj << /parent 4479 0 r /dest (g1.1832402) /prev 4493 0 r /title (14.6.3 using the input capture unit) >> endobj 4482 0 obj << /first 4483 0 r /parent 4334 0 r /next 4479 0 r /dest (g1.1932414) /count -5 /last 4484 0 r /prev 4485 0 r /title (14.5 modes of operation) >> endobj 4483 0 obj << /parent 4482 0 r /next 4492 0 r /dest (g1.1932525) /title (14.5.1 normal 8-bit mode) >> endobj 4484 0 obj << /parent 4482 0 r /dest (g1.1932610) /prev 4490 0 r /title (14.5.5 16-bit input capture mode) >> endobj 4485 0 obj << /parent 4334 0 r /next 4482 0 r /dest (g1.1832298) /prev 4486 0 r /title (14.4 counter unit) >> endobj 4486 0 obj << /parent 4334 0 r /next 4485 0 r /dest (g1.1832287) /prev 4487 0 r /title (14.3 timer/counter clock sources) >> endobj 4487 0 obj << /first 4488 0 r /parent 4334 0 r /next 4486 0 r /dest (g1.1832220) /count -2 /last 4489 0 r /prev 4335 0 r /title (14.2 overview) >> endobj 4488 0 obj << /parent 4487 0 r /next 4489 0 r /dest (g1.1832236) /title (14.2.1 registers) >> endobj 4489 0 obj << /parent 4487 0 r /dest (g1.1832259) /prev 4488 0 r /title (14.2.2 definitions) >> endobj 4490 0 obj << /parent 4482 0 r /next 4484 0 r /dest (g1.1987867) /prev 4491 0 r /title (14.5.4 8-bit input capture mode) >> endobj 4491 0 obj << /parent 4482 0 r /next 4490 0 r /dest (g1.1932593) /prev 4492 0 r /title (14.5.3 16-bit mode) >> endobj 4492 0 obj << /parent 4482 0 r /next 4491 0 r /dest (g1.1932542) /prev 4483 0 r /title (14.5.2 clear timer on compare match \(ctc\) 8-bit mode) >> endobj 4493 0 obj << /parent 4479 0 r /next 4481 0 r /dest (g1.1832399) /prev 4480 0 r /title (14.6.2 noise canceler) >> endobj 4494 0 obj << /parent 4336 0 r /next 4472 0 r /dest (g1.1833165) /prev 4495 0 r /title (14.10.6 timsk - timer/counter0 interrupt mask register) >> endobj 4495 0 obj << /parent 4336 0 r /next 4494 0 r /dest (g1.1833064) /prev 4496 0 r /title (14.10.5 ocr0b - timer/counter0 output compare register b) >> endobj 4496 0 obj << /parent 4336 0 r /next 4495 0 r /dest (g1.1832963) /prev 4497 0 r /title (14.10.4 ocr0a - timer/counter0 output compare register a) >> endobj 4497 0 obj << /parent 4336 0 r /next 4496 0 r /dest (g1.1832853) /prev 4498 0 r /title (14.10.3 tcnt0h - timer/counter0 register high byte) >> endobj 4498 0 obj << /parent 4336 0 r /next 4497 0 r /dest (g1.1832748) /prev 4471 0 r /title (14.10.2 tcnt0l - timer/counter0 register low byte) >> endobj 4499 0 obj << /parent 4333 0 r /next 4500 0 r /dest (g1.1980384) /title (15.1.1 pllcsr - pll control and status register) >> endobj 4500 0 obj << /parent 4333 0 r /dest (g1.1839500) /prev 4499 0 r /title (15.1.2 tccr1b - timer/counter1 control register b) >> endobj 4501 0 obj << /parent 4331 0 r /next 4333 0 r /dest (g1.1839401) /prev 4332 0 r /title (15.0.2 prescaler initialization for asynchronous mode) >> endobj 4502 0 obj << /parent 4330 0 r /next 4541 0 r /dest (g1.1842622) /title (16.11.1 tccr1a - timer/counter1 control register a) >> endobj 4503 0 obj << /parent 4330 0 r /dest (g1.1844737) /prev 4530 0 r /title (16.11.14 dt1 - timer/counter1 dead time value) >> endobj 4504 0 obj << /first 4505 0 r /parent 4328 0 r /next 4330 0 r /dest (g1.1842402) /count -1 /last 4505 0 r /prev 4506 0 r /title (16.10 accessing 10-bit registers) >> endobj 4505 0 obj << /parent 4504 0 r /dest (g1.1842617) /title (16.10.1 reusing the temporary high byte register) >> endobj 4506 0 obj << /first 4507 0 r /parent 4328 0 r /next 4504 0 r /dest (g1.1842382) /count -2 /last 4508 0 r /prev 4509 0 r /title (16.9 fault protection unit) >> endobj 4507 0 obj << /parent 4506 0 r /next 4508 0 r /dest (g1.1842392) /title (16.9.1 fault protection trigger source) >> endobj 4508 0 obj << /parent 4506 0 r /dest (g1.1842398) /prev 4507 0 r /title (16.9.2 noise canceler) >> endobj 4509 0 obj << /parent 4328 0 r /next 4506 0 r /dest (g1.1842347) /prev 4510 0 r /title (16.8 timer/counter timing diagrams) >> endobj 4510 0 obj << /first 4511 0 r /parent 4328 0 r /next 4509 0 r /dest (g1.1841855) /count -4 /last 4512 0 r /prev 4513 0 r /title (16.7 modes of operation) >> endobj 4511 0 obj << /parent 4510 0 r /next 4529 0 r /dest (g1.1841873) /title (16.7.1 normal mode) >> endobj 4512 0 obj << /parent 4510 0 r /dest (g1.1842201) /prev 4528 0 r /title (16.7.4 pwm6 mode) >> endobj 4513 0 obj << /first 4514 0 r /parent 4328 0 r /next 4510 0 r /dest (g1.1841829) /count -1 /last 4514 0 r /prev 4515 0 r /title (16.6 compare match output unit) >> endobj 4514 0 obj << /parent 4513 0 r /dest (g1.1877093) /title (16.6.1 compare output mode and waveform generation) >> endobj 4515 0 obj << /parent 4328 0 r /next 4513 0 r /dest (g1.1841808) /prev 4516 0 r /title (16.5 dead time generator) >> endobj 4516 0 obj << /first 4517 0 r /parent 4328 0 r /next 4515 0 r /dest (g1.1841777) /count -3 /last 4518 0 r /prev 4519 0 r /title (16.4 output compare unit) >> endobj 4517 0 obj << /parent 4516 0 r /next 4527 0 r /dest (g1.1841799) /title (16.4.1 force output compare) >> endobj 4518 0 obj << /parent 4516 0 r /dest (g1.1841803) /prev 4527 0 r /title (16.4.3 using the output compare unit) >> endobj 4519 0 obj << /first 4520 0 r /parent 4328 0 r /next 4516 0 r /dest (g1.1980786) /count -1 /last 4520 0 r /prev 4521 0 r /title (16.3 counter unit) >> endobj 4520 0 obj << /parent 4519 0 r /dest (g1.1841775) /title (16.3.1 counter initialization for asynchronous mode) >> endobj 4521 0 obj << /first 4522 0 r /parent 4328 0 r /next 4519 0 r /dest (g1.1841684) /count -5 /last 4523 0 r /prev 4329 0 r /title (16.2 overview) >> endobj 4522 0 obj << /parent 4521 0 r /next 4526 0 r /dest (g1.1841700) /title (16.2.1 speed) >> endobj 4523 0 obj << /parent 4521 0 r /dest (g1.1841727) /prev 4524 0 r /title (16.2.5 definitions) >> endobj 4524 0 obj << /parent 4521 0 r /next 4523 0 r /dest (g1.1841715) /prev 4525 0 r /title (16.2.4 synchronization) >> endobj 4525 0 obj << /parent 4521 0 r /next 4524 0 r /dest (g1.1841710) /prev 4526 0 r /title (16.2.3 registers) >> endobj 4526 0 obj << /parent 4521 0 r /next 4525 0 r /dest (g1.1841705) /prev 4522 0 r /title (16.2.2 accuracy) >> endobj 4527 0 obj << /parent 4516 0 r /next 4518 0 r /dest (g1.1841801) /prev 4517 0 r /title (16.4.2 compare match blocking by tcnt1 write) >> endobj 4528 0 obj << /parent 4510 0 r /next 4512 0 r /dest (g1.1842048) /prev 4529 0 r /title (16.7.3 phase and frequency correct pwm mode) >> endobj 4529 0 obj << /parent 4510 0 r /next 4528 0 r /dest (g1.1841892) /prev 4511 0 r /title (16.7.2 ifast pwm mode) >> endobj 4530 0 obj << /parent 4330 0 r /next 4503 0 r /dest (g1.1844644) /prev 4531 0 r /title (16.11.13 tifr - timer/counter1 interrupt flag register) >> endobj 4531 0 obj << /parent 4330 0 r /next 4530 0 r /dest (g1.1908675) /prev 4532 0 r /title (16.11.12 timsk - timer/counter1 interrupt mask register) >> endobj 4532 0 obj << /parent 4330 0 r /next 4531 0 r /dest (g1.1982303) /prev 4533 0 r /title (16.11.11 ocr1d - timer/counter1 output compare register d) >> endobj 4533 0 obj << /parent 4330 0 r /next 4532 0 r /dest (g1.1844372) /prev 4534 0 r /title (16.11.10 ocr1c - timer/counter1 output compare register c) >> endobj 4534 0 obj << /parent 4330 0 r /next 4533 0 r /dest (g1.1844282) /prev 4535 0 r /title (16.11.9 ocr1b - timer/counter1 output compare register b) >> endobj 4535 0 obj << /parent 4330 0 r /next 4534 0 r /dest (g1.1844192) /prev 4536 0 r /title (16.11.8 ocr1a - timer/counter1 output compare register a) >> endobj 4536 0 obj << /parent 4330 0 r /next 4535 0 r /dest (g1.1844098) /prev 4537 0 r /title (16.11.7 tc1h - timer/counter1 high byte) >> endobj 4537 0 obj << /parent 4330 0 r /next 4536 0 r /dest (g1.1844010) /prev 4538 0 r /title (16.11.6 tcnt1 - timer/counter1) >> endobj 4538 0 obj << /parent 4330 0 r /next 4537 0 r /dest (g1.1843876) /prev 4539 0 r /title (16.11.5 tccr1e - timer/counter1 control register e) >> endobj 4539 0 obj << /parent 4330 0 r /next 4538 0 r /dest (g1.1843667) /prev 4540 0 r /title (16.11.4 tccr1d - timer/counter1 control register d) >> endobj 4540 0 obj << /parent 4330 0 r /next 4539 0 r /dest (g1.1843399) /prev 4541 0 r /title (16.11.3 tccr1c - timer/counter1 control register c) >> endobj 4541 0 obj << /parent 4330 0 r /next 4540 0 r /dest (g1.1843045) /prev 4502 0 r /title (16.11.2 tccr1b - timer/counter1 control register b) >> endobj 4542 0 obj << /parent 4327 0 r /next 4559 0 r /dest (g1.1585346) /title (17.5.1 usidr - usi data register) >> endobj 4543 0 obj << /parent 4327 0 r /dest (g1.1982363) /prev 4557 0 r /title (17.5.5 usipp - usi pin position) >> endobj 4544 0 obj << /first 4545 0 r /parent 4325 0 r /next 4327 0 r /dest (g1.1585331) /count -5 /last 4546 0 r /prev 4547 0 r /title (17.4 alternative usi usage) >> endobj 4545 0 obj << /parent 4544 0 r /next 4556 0 r /dest (g1.1585333) /title (17.4.1 half-duplex asynchronous data transfer) >> endobj 4546 0 obj << /parent 4544 0 r /dest (g1.1585341) /prev 4554 0 r /title (17.4.5 software interrupt) >> endobj 4547 0 obj << /first 4548 0 r /parent 4325 0 r /next 4544 0 r /dest (g1.1585187) /count -5 /last 4549 0 r /prev 4550 0 r /title (17.3 functional descriptions) >> endobj 4548 0 obj << /parent 4547 0 r /next 4553 0 r /dest (g1.1585188) /title (17.3.1 three-wire mode) >> endobj 4549 0 obj << /parent 4547 0 r /dest (g1.1585319) /prev 4551 0 r /title (17.3.5 start condition detector) >> endobj 4550 0 obj << /parent 4325 0 r /next 4547 0 r /dest (g1.1585167) /prev 4326 0 r /title (17.2 overview) >> endobj 4551 0 obj << /parent 4547 0 r /next 4549 0 r /dest (g1.1585281) /prev 4552 0 r /title (17.3.4 two-wire mode) >> endobj 4552 0 obj << /parent 4547 0 r /next 4551 0 r /dest (g1.1585263) /prev 4553 0 r /title (17.3.3 spi slave operation example) >> endobj 4553 0 obj << /parent 4547 0 r /next 4552 0 r /dest (g1.1585220) /prev 4548 0 r /title (17.3.2 spi master operation example) >> endobj 4554 0 obj << /parent 4544 0 r /next 4546 0 r /dest (g1.1585339) /prev 4555 0 r /title (17.4.4 edge triggered external interrupt) >> endobj 4555 0 obj << /parent 4544 0 r /next 4554 0 r /dest (g1.1585337) /prev 4556 0 r /title (17.4.3 12-bit timer/counter) >> endobj 4556 0 obj << /parent 4544 0 r /next 4555 0 r /dest (g1.1585335) /prev 4545 0 r /title (17.4.2 4-bit counter) >> endobj 4557 0 obj << /parent 4327 0 r /next 4543 0 r /dest (g1.1585535) /prev 4558 0 r /title (17.5.4 usicr - usi control register) >> endobj 4558 0 obj << /parent 4327 0 r /next 4557 0 r /dest (g1.1629799) /prev 4559 0 r /title (17.5.3 usisr - usi status register) >> endobj 4559 0 obj << /parent 4327 0 r /next 4558 0 r /dest (g1.1629810) /prev 4542 0 r /title (17.5.2 usibr - usi buffer register) >> endobj 4560 0 obj << /parent 4324 0 r /dest (g1.1857989) /title (18.2.1 acsrb - analog comparator control and status register b) >> endobj 4561 0 obj << /parent 4323 0 r /dest (g1.1982371) /title (18.1.1 acsra - analog comparator control and status register a) >> endobj 4562 0 obj << /parent 4321 0 r /next 4585 0 r /dest (g1.1984222) /title (19.10.1 admux - adc multiplexer selection register) >> endobj 4563 0 obj << /parent 4321 0 r /dest (g1.1861237) /prev 4580 0 r /title (19.10.6 didr1 - digital input disable register 1) >> endobj 4564 0 obj << /parent 4319 0 r /next 4321 0 r /dest (g1.1984214) /prev 4565 0 r /title (19.9 temperature measurement) >> endobj 4565 0 obj << /first 4566 0 r /parent 4319 0 r /next 4564 0 r /dest (g1.1202586) /count -3 /last 4567 0 r /prev 4568 0 r /title (19.8 adc conversion result) >> endobj 4566 0 obj << /parent 4565 0 r /next 4579 0 r /dest (g1.1202591) /title (19.8.1 single ended conversion) >> endobj 4567 0 obj << /parent 4565 0 r /dest (g1.1654857) /prev 4579 0 r /title (19.8.3 bipolar differential conversion) >> endobj 4568 0 obj << /first 4569 0 r /parent 4319 0 r /next 4565 0 r /dest (g1.1202518) /count -3 /last 4570 0 r /prev 4571 0 r /title (19.7 adc noise canceler) >> endobj 4569 0 obj << /parent 4568 0 r /next 4578 0 r /dest (g1.1202525) /title (19.7.1 analog input circuitry) >> endobj 4570 0 obj << /parent 4568 0 r /dest (g1.1202560) /prev 4578 0 r /title (19.7.3 adc accuracy definitions) >> endobj 4571 0 obj << /first 4572 0 r /parent 4319 0 r /next 4568 0 r /dest (g1.1202487) /count -2 /last 4573 0 r /prev 4574 0 r /title (19.6 changing channel or reference selection) >> endobj 4572 0 obj << /parent 4571 0 r /next 4573 0 r /dest (g1.1202504) /title (19.6.1 adc input channels) >> endobj 4573 0 obj << /parent 4571 0 r /dest (g1.1202509) /prev 4572 0 r /title (19.6.2 adc voltage reference) >> endobj 4574 0 obj << /parent 4319 0 r /next 4571 0 r /dest (g1.1202404) /prev 4575 0 r /title (19.5 prescaling and conversion timing) >> endobj 4575 0 obj << /parent 4319 0 r /next 4574 0 r /dest (g1.1859626) /prev 4576 0 r /title (19.4 starting a conversion) >> endobj 4576 0 obj << /parent 4319 0 r /next 4575 0 r /dest (g1.1202386) /prev 4577 0 r /title (19.3 operation) >> endobj 4577 0 obj << /parent 4319 0 r /next 4576 0 r /dest (g1.1982378) /prev 4320 0 r /title (19.2 overview) >> endobj 4578 0 obj << /parent 4568 0 r /next 4570 0 r /dest (g1.1202544) /prev 4569 0 r /title (19.7.2 analog noise canceling techniques) >> endobj 4579 0 obj << /parent 4565 0 r /next 4567 0 r /dest (g1.1653064) /prev 4566 0 r /title (19.8.2 unipolar differential conversion) >> endobj 4580 0 obj << /parent 4321 0 r /next 4563 0 r /dest (g1.1861149) /prev 4581 0 r /title (19.10.5 didr0 - digital input disable register 0) >> endobj 4581 0 obj << /parent 4321 0 r /next 4580 0 r /dest (g1.1203708) /prev 4582 0 r /title (19.10.4 adcsrb - adc control and status register b) >> endobj 4582 0 obj << /first 4583 0 r /parent 4321 0 r /next 4581 0 r /dest (g1.1873455) /count -2 /last 4584 0 r /prev 4585 0 r /title (19.10.3 adcl and adch - the adc data register) >> endobj 4583 0 obj << /parent 4582 0 r /next 4584 0 r /dest (g1.1203374) /title (19.10.3.1 adlar = 0) >> endobj 4584 0 obj << /parent 4582 0 r /dest (g1.1203537) /prev 4583 0 r /title (19.10.3.2 adlar = 1) >> endobj 4585 0 obj << /parent 4321 0 r /next 4582 0 r /dest (g1.1907204) /prev 4562 0 r /title (19.10.2 adcsra - adc control and status register a) >> endobj 4586 0 obj << /parent 4318 0 r /dest (g1.1519804) /title (20.6.1 dwdr - debugwire data register) >> endobj 4587 0 obj << /parent 4316 0 r /next 4318 0 r /dest (g1.1519469) /prev 4588 0 r /title (20.5 limitations of debugwire) >> endobj 4588 0 obj << /parent 4316 0 r /next 4587 0 r /dest (g1.1522121) /prev 4589 0 r /title (20.4 software break points) >> endobj 4589 0 obj << /parent 4316 0 r /next 4588 0 r /dest (g1.1519455) /prev 4590 0 r /title (20.3 physical interface) >> endobj 4590 0 obj << /parent 4316 0 r /next 4589 0 r /dest (g1.1519452) /prev 4317 0 r /title (20.2 overview) >> endobj 4591 0 obj << /parent 4315 0 r /dest (g1.1985058) /title (21.2.1 spmcsr - store program memory control and status register) >> endobj 4592 0 obj << /first 4593 0 r /parent 4313 0 r /next 4315 0 r /dest (g1.1522914) /count -4 /last 4594 0 r /prev 4595 0 r /title (21.1 addressing the flash during self-programming) >> endobj 4593 0 obj << /parent 4592 0 r /next 4598 0 r /dest (g1.1555515) /title (21.1.1 eeprom write prevents writing to spmcsr) >> endobj 4594 0 obj << /parent 4592 0 r /dest (g1.1555716) /prev 4597 0 r /title (21.1.4 programming time for flash when using spm) >> endobj 4595 0 obj << /parent 4313 0 r /next 4592 0 r /dest (g1.1522350) /prev 4596 0 r /title (21.0.3 performing a page write) >> endobj 4596 0 obj << /parent 4313 0 r /next 4595 0 r /dest (g1.1522346) /prev 4314 0 r /title (21.0.2 filling the temporary buffer \(page loading\)) >> endobj 4597 0 obj << /parent 4592 0 r /next 4594 0 r /dest (g1.1555990) /prev 4598 0 r /title (21.1.3 preventing flash corruption) >> endobj 4598 0 obj << /parent 4592 0 r /next 4597 0 r /dest (g1.1555518) /prev 4593 0 r /title (21.1.2 reading the fuse and lock bits from software) >> endobj 4599 0 obj << /parent 4312 0 r /next 4600 0 r /dest (g1.1940354) /title (22.8.1 serial programming algorithm) >> endobj 4600 0 obj << /parent 4312 0 r /dest (g1.1771943) /prev 4599 0 r /title (22.8.2 serial programming instruction set) >> endobj 4601 0 obj << /first 4602 0 r /parent 4310 0 r /next 4312 0 r /dest (g1.1863880) /count -14 /last 4603 0 r /prev 4604 0 r /title (22.7 parallel programming) >> endobj 4602 0 obj << /parent 4601 0 r /next 4622 0 r /dest (g1.1863881) /title (22.7.1 enter programming mode) >> endobj 4603 0 obj << /parent 4601 0 r /dest (g1.1940195) /prev 4611 0 r /title (22.7.14 reading the calibration byte) >> endobj 4604 0 obj << /first 4605 0 r /parent 4310 0 r /next 4601 0 r /dest (g1.1985304) /count -1 /last 4605 0 r /prev 4606 0 r /title (22.6 parallel programming parameters, pin mapping, and commands) >> endobj 4605 0 obj << /parent 4604 0 r /dest (g1.1863502) /title (22.6.1 signal names) >> endobj 4606 0 obj << /parent 4310 0 r /next 4604 0 r /dest (g1.1519867) /prev 4607 0 r /title (22.5 page size) >> endobj 4607 0 obj << /parent 4310 0 r /next 4606 0 r /dest (g1.1905964) /prev 4608 0 r /title (22.4 calibration byte) >> endobj 4608 0 obj << /parent 4310 0 r /next 4607 0 r /dest (g1.1207865) /prev 4609 0 r /title (22.3 signature bytes) >> endobj 4609 0 obj << /first 4610 0 r /parent 4310 0 r /next 4608 0 r /dest (g1.1207539) /count -1 /last 4610 0 r /prev 4311 0 r /title (22.2 fuse bytes) >> endobj 4610 0 obj << /parent 4609 0 r /dest (g1.1207863) /title (22.2.1 latching of fuses) >> endobj 4611 0 obj << /parent 4601 0 r /next 4603 0 r /dest (g1.1940284) /prev 4612 0 r /title (22.7.13 reading the signature bytes) >> endobj 4612 0 obj << /parent 4601 0 r /next 4611 0 r /dest (g1.1864079) /prev 4613 0 r /title (22.7.12 reading the fuse and lock bits) >> endobj 4613 0 obj << /parent 4601 0 r /next 4612 0 r /dest (g1.1940207) /prev 4614 0 r /title (22.7.11 programming the lock bits) >> endobj 4614 0 obj << /parent 4601 0 r /next 4613 0 r /dest (g1.1864056) /prev 4615 0 r /title (22.7.10 programming the extended fuse bits) >> endobj 4615 0 obj << /parent 4601 0 r /next 4614 0 r /dest (g1.1985317) /prev 4616 0 r /title (22.7.9 programming the fuse high bits) >> endobj 4616 0 obj << /parent 4601 0 r /next 4615 0 r /dest (g1.1864038) /prev 4617 0 r /title (22.7.8 programming the fuse low bits) >> endobj 4617 0 obj << /parent 4601 0 r /next 4616 0 r /dest (g1.1864028) /prev 4618 0 r /title (22.7.7 reading the eeprom) >> endobj 4618 0 obj << /parent 4601 0 r /next 4617 0 r /dest (g1.1864014) /prev 4619 0 r /title (22.7.6 reading the flash) >> endobj 4619 0 obj << /parent 4601 0 r /next 4618 0 r /dest (g1.1863988) /prev 4620 0 r /title (22.7.5 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